1. Field of the Invention
The invention relates in general to a method of fabricating an integrated circuit, and more particularly, to a method of fabricating a shallow trench isolation (ST1).
2. Description of the Related Art
In an integrated circuit shallow trench isolations are commonly used for insulating adjacent devices such as metal-oxide semiconductors (MOS) or active regions. In a conventional method of fabricating a shallow trench isolation, typically, an anisotropic dry etching is used to form a trench in a semiconductor substrate. By filling the trench with an oxide layer, the shallow trench isolation is formed.
A conventional method of fabricating a shallow trench isolation is described with accordance of the accompanying drawings FIG. 1A to FIG. 1E. In FIG. 1A, a pad oxide layer 102 with a thickness of about 100 to 500 .ANG. is formed on a semiconductor substrate 100. On the pad oxide layer 102, a mask layer 104 is formed, for example, a silicon nitride layer formed by chemical vapor deposition (CVD). The thickness of the mask layer 104 is about 1000 to 3000 .ANG.. Using photolithography and etching, a photo-resist layer 106 with an opening exposing a part of the mask layer 104 is formed on the mask layer 104. The mask layer 104 exposed within the opening is then removed to expose the pad oxide layer 102. The photo-resist layer 106 is removed. Using the mask layer 104 as a mask, the exposed pad oxide layer 102 and a part of the underlying substrate 100 are removed by dry etch, so that a trench is formed 108. The regions of the semiconductor 100 covered the pad oxide layer 102 which is protected from being removed by the mask layer 104 is thus defined as an active region.
In FIG. 1C, a liner oxide layer is formed on the surface of the trench 108. The liner oxide layer joins the pad oxide layer 102 as the oxide layer denoted as 102a in the figure. An insulating layer, for example, a silicon oxide layer, is formed to cover the mask layer 104 and to fill the trench 108. The insulating layer is then polished until the mask layer 104 is exposed, so that an insulating plug 110 is formed within the trench 118.
In FIG. 1D, the mask layer 104 and the oxide layer 102a under the mask layer 104 are removed by isotropic wet etching with hydrogen fluoride (HF) as an etchant. After the removing process, the active region of the substrate 100 is exposed. The material of the insulating plug 110 and the oxide layer 102a are typically softer and easier to be removed than the material of the mask layer 104. Therefore, during the removing process a part of the side wall of the insulating plug 110 and the oxide layer 102a on the active region are removed while removing the mask layer 104. Furthermore, the topmost area of the liner oxide layer on the surface of the trench 108 is removed. As a consequence, the rim of the insulation plug 110 and the oxide layer 102a between the insulating plug 110 and the active region have a lower surface level than the active region of the substrate 100.
In FIG. 1E, to complete the formation of the shallow trench isolation, a polishing step is performed. The insulating plug 110 is polished by chemical-mechanical polishing until having a same surface level of the substrate 100. The polished insulating plug 110 is used as the shallow trench isolation and is denoted as 110a in the figure.
As mentioned above, the oxide between the shallow trench isolation 110a and the active region has a lower surface level than the active region of the substrate 100. When the shallow trench isolation 110a is formed, a notch, or a shoulder portion 112 is formed between the active region of the substrate 100 and the shallow trench isolation 110a. In the subsequent process of forming a gate oxide layer, a non-uniform gate oxide with poor quality is formed due to the formation of the shoulder portion 112. For a device formed on the gate oxide layer with a poor quality, the threshold voltage is seriously affected. During the metallization process, some metal interconnect extends over both the active region and the isolation structure. With the formation of the shoulder portion 112, an unwanted electrical couple is very likely to occur. Furthermore, in a subsequent ion implantation process, the shoulder portion will cause implanted ions accumulation. A kink effect is likely to occur to cause an abnormal sub-threshold current.